1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to circuits and methods of operating circuits that allow for the storage of a signal value in both operational and sleep modes.
2. Description of the Prior Art
In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency attention is also being turned to reducing static power consumption, i.e. power loss due to leakage currents. One way of addressing this is to provide the circuit with a sleep mode so that it is in effect powered down during these non-operational periods. To reduce static power during these sleep periods, many circuit designs are now making use of on-chip power gating which allows rapid transitions between sleep and functional modes. This power gating is achieved by inserting power transistors between the targeted circuitry and Vdd creating a “virtual” Vdd rail, or by inserting power transistors between the targeted circuitry and Vss creating a “virtual” Vss rail. To enter a low leakage mode, the power transistors are turned off and the leakage of the design is limited by the leakage of the power transistors. Since the power transistors can be made to be high Vt (threshold voltage), and since the width of the power transistors can be much less than the width of the active devices in the circuit, leakage currents can be dramatically reduced. Thus, when the power transistors are turned off the virtual power rail at their output floats and the circuit is powered down.
Although this results in substantial power savings it also results in a loss of state within the targeted circuitry. If it is desired that the circuit retain state during sleep mode, data retention circuits such as special data retention flip-flops must be used within the design. Such a mode of operation allows the stored signal values to be securely held in a small portion of the circuitry whilst the remainder of the circuitry is powered down for leakage reduction purposes. When power is resumed, the saved signal value is restored and operation continues.
A common prior art approach to data retention is to provide an additional third storage or balloon latch that is not in the data pathway of the other two latches of a flip flop and to store data in this third latch during sleep mode. This latch has its own power supply and can be built of high threshold components. Such a system is described in “A 1V High Speed MTCMOS Circuit Scheme for Power-Down Application Circuits” IEEE Journal of Solid-State Circuits, Vol 32, No 6, June 1997. A disadvantage of this approach is that the balloon latches consume considerable additional circuit area.
It has also been proposed for sense amplifier flip-flops and hybrid latch flip-flops which have associated scan cells that operate in accordance with the level sensitive scan design methodology to reuse the scan cells for data retention during a power down mode of operation. Whilst this approach reduces the increase in circuit overhead associated with providing the data retention capability, it does require control of the three clock signals of the sense amplifier flip-flops or hybrid latch flip-flops with their known disadvantages in terms of speed, power consumption and other factors. It is also only applicable to flip flops having dedicated scan latches.
“Lower Power Integrated Scan-Retention Mechanism” ISPLED August 2002, also addresses this problem.
Co pending U.S. application Ser. No. 11/088268 having the same assignee as this patent also addresses this problem.